Acerca de este Curso

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Certificado para compartir
Obtén un certificado al finalizar
100 % en línea
Comienza de inmediato y aprende a tu propio ritmo.
Fechas límite flexibles
Restablece las fechas límite en función de tus horarios.
Nivel intermedio
Aprox. 36 horas para completar
Inglés (English)
Subtítulos: Francés (French), Portugués (de Brasil), Ruso (Russian), Inglés (English), Español (Spanish)

Habilidades que obtendrás

Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
Certificado para compartir
Obtén un certificado al finalizar
100 % en línea
Comienza de inmediato y aprende a tu propio ritmo.
Fechas límite flexibles
Restablece las fechas límite en función de tus horarios.
Nivel intermedio
Aprox. 36 horas para completar
Inglés (English)
Subtítulos: Francés (French), Portugués (de Brasil), Ruso (Russian), Inglés (English), Español (Spanish)

ofrecido por

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Universidad de Colorado en Boulder

Comienza a trabajar para obtener tu maestría

Este curso es parte del Master of Science in Electrical Engineering completamente en línea de Universidad de Colorado en Boulder. Si eres aceptado en el programa completo, tus cursos cuentan para tu título.

Programa - Qué aprenderás en este curso

Semana
1

Semana 1

8 horas para completar

Basics of VHDL

8 horas para completar
10 videos (Total 48 minutos), 2 lecturas, 6 cuestionarios
10 videos
Why Learn VHDL?1m
FPGA Design Flow3m
Intro to VHDL: Finite State Machine3m
How to speak VHDL, first phrases6m
VHDL Assignments, Operators, Types3m
VHDL Rules and Syntax, Interface Ports3m
VHDL in ModelSim: Download and Install3m
VHDL in ModelSim: Adding to your Toolkit6m
Submitting VHDL Programming Assignments11m
2 lecturas
Misson 2-001: Week 1 Readings2h
Files for Week 1 Programming Assignments10m
2 ejercicios de práctica
VHDL Find the Code Errors30m
Module 1 Quiz30m
Semana
2

Semana 2

12 horas para completar

VHDL Logic Design Techniques

12 horas para completar
10 videos (Total 52 minutos), 2 lecturas, 6 cuestionarios
10 videos
Combinatorial Circuits4m
Synchronous Logic: Latches and Flip Flops4m
Synchronous Logic: Counters and Registers6m
Buses and Tristate Buffers3m
Modular Designs: Components, Generate and Loops in VHDL3m
Test Benches in VHDL: Combinatorial8m
Test Benches in VHDL: Synchronous5m
Memory in VHDL7m
Finite State Machines in VHDL8m
2 lecturas
Week 2 Readings2h
Files for Week 2 Programming Assignments10m
1 ejercicio de práctica
Module 2 Quiz30m
Semana
3

Semana 3

7 horas para completar

Basics of Verilog

7 horas para completar
9 videos (Total 92 minutos), 2 lecturas, 6 cuestionarios
9 videos
Your First Verilog phrase11m
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12m
Verilog Statements and Operators16m
Verilog Modules, Port Modes and Data Types10m
Verilog Structure10m
Testing with ModelSim5m
Verilog Evaluation11m
Submitting Verilog Programming Assignments10m
2 lecturas
Week 3 Readings1h 10m
Files for Week 3 Programming Assignments10m
2 ejercicios de práctica
Verilog Find the Errors20m
Module 3 Quiz30m
Semana
4

Semana 4

10 horas para completar

Verilog and System Verilog Design Techniques

10 horas para completar
10 videos (Total 48 minutos), 2 lecturas, 6 cuestionarios
10 videos
Combinatorial Circuits5m
Synchronous Logic: Latches and Flip Flops3m
Synchronous Logic: Counters and Registers5m
Buses and Tristate Buffers3m
Modular Design in Verilog3m
Testbenches in Verilog7m
Testbenches in Verilog II2m
Memory with Verilog4m
Verilog Finite State Machines7m
2 lecturas
Week 4 Readings15m
Files for Week 4 Programming Assignments10m
1 ejercicio de práctica
Module 4 Quiz30m

Reseñas

Principales reseñas sobre HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN

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Acerca de Programa especializado: FPGA Design for Embedded Systems

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include: Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards....
FPGA Design for Embedded Systems

Preguntas Frecuentes

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