This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.
Hardware Description Languages for FPGA Design
ofrecido por
Hardware Description Languages for FPGA Design
Habilidades que obtendrás
100 % en línea
Fechas límite flexibles
Nivel intermedio
Aprox. 25 horas para completar
Inglés (English)
Programa - Qué aprenderás en este curso
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
Principales revisiones sobre Hardware Description Languages for FPGA Design
Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.
Instructores
Timothy Scherr
Senior Instructor and Professor of Engineering Practice
Benjamin Spriggs
Lecturer and Scholar of Engineering PracticeComienza a trabajar para obtener tu maestría
Acerca de Universidad de Colorado en Boulder
Preguntas Frecuentes
¿Cuándo podré acceder a las lecciones y tareas?
Una vez que te inscribes para obtener un Certificado, tendrás acceso a todos los videos, cuestionarios y tareas de programación (si corresponde). Las tareas calificadas por compañeros solo pueden enviarse y revisarse una vez que haya comenzado tu sesión. Si eliges explorar el curso sin comprarlo, es posible que no puedas acceder a determinadas tareas.
¿Qué recibiré si compro el Certificado?
Cuando compras un Certificado, obtienes acceso a todos los materiales del curso, incluidas las tareas calificadas. Una vez que completes el curso, se añadirá tu Certificado electrónico a la página Logros. Desde allí, puedes imprimir tu Certificado o añadirlo a tu perfil de LinkedIn. Si solo quieres leer y visualizar el contenido del curso, puedes participar del curso como oyente sin costo.
¿Cuál es la política de reembolsos?
¿Hay ayuda económica disponible?
¿Tienes más preguntas? Visita el Centro de Ayuda al Alumno.
