Acerca de este Curso
4.8
30 calificaciones
5 revisiones
You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....
Globe

Cursos 100 % en línea

Comienza de inmediato y aprende a tu propio ritmo.
Calendar

Fechas límite flexibles

Restablece las fechas límite en función de tus horarios.
Intermediate Level

Nivel intermedio

Clock

Approx. 21 hours to complete

Sugerido: 6 hours/week...
Comment Dots

English

Subtítulos: English...
Globe

Cursos 100 % en línea

Comienza de inmediato y aprende a tu propio ritmo.
Calendar

Fechas límite flexibles

Restablece las fechas límite en función de tus horarios.
Intermediate Level

Nivel intermedio

Clock

Approx. 21 hours to complete

Sugerido: 6 hours/week...
Comment Dots

English

Subtítulos: English...

Programa - Qué aprenderás en este curso

Week
1
Clock
1 hora para completar

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course....
Reading
2 videos (Total: 23 min), 2 readings, 1 quiz
Video2 videos
Two Tools Tutorial4m
Reading2 lecturas
Syllabus10m
Tools For This Course10m
Quiz1 ejercicio de práctica
Demographics Survey5m
Clock
3 horas para completar

ASIC Placement

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks....
Reading
9 videos (Total: 163 min), 2 readings
Video9 videos
Wirelength Estimation15m
Simple Iterative Improvement Placement12m
Iterative Improvement with Hill Climbing15m
Simulated Annealing Placement27m
Analytical Placement: Quadratic Wirelength Model14m
Analytical Placement: Quadratic Placement26m
Analytical Placement: Recursive Partitioning18m
Analytical Placement: Recursive Partitioning Example16m
Reading2 lecturas
Week 1 Overview10m
Week 1 Assignments10m
Week
2
Clock
6 horas para completar

Technology Mapping

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD....
Reading
6 videos (Total: 102 min), 2 readings, 2 quizzes
Video6 videos
Technology Mapping as Tree Covering29m
Technology Mapping—Tree-ifying the Netlist13m
Technology Mapping—Recursive Matching9m
Technology Mapping—Minimum Cost Covering16m
Technology Mapping—Detailed Covering Example14m
Reading2 lecturas
Week 2 Overview10m
Week 2 Assignments10m
Quiz1 ejercicio de práctica
Problem Set #1m
Week
3
Clock
4 horas para completar

ASIC Routing

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment....
Reading
9 videos (Total: 145 min), 2 readings, 1 quiz
Video9 videos
Maze Routing: 2-Point Nets in 1 Layer16m
Maze Routing: Multi-Point Nets12m
Maze Routing: Multi-Layer Routing12m
Maze Routing: Non-Uniform Grid Costs14m
Implementation Mechanics: How Expansion Works23m
Implementation Mechanics: Data Structures & Constraints18m
Implementation Mechanics: Depth First Search14m
From Detailed Routing to Global Routing15m
Reading2 lecturas
Week 3 Overview10m
Week 3 Assignments10m
Quiz1 ejercicio de práctica
Problem Set #2m
Week
4
Clock
7 horas para completar

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design....
Reading
8 videos (Total: 148 min), 2 readings, 2 quizzes
Video8 videos
Logic-Level Timing: Basic Assumptions & Models30m
Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks27m
Logic-Level Timing: A Detailed Example and the Role of Slack10m
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths26m
Interconnect Timing: Electrical Models of Wire Delay16m
Interconnect Timing: The Elmore Delay Model14m
Interconnect Timing: Elmore Delay Examples14m
Reading2 lecturas
Week 4 Overview10m
Week 4 Assignments10m
Quiz1 ejercicio de práctica
Problem Set #3m

Instructor

Rob A. Rutenbar

Adjunct Professor
Department of Computer Science

Acerca de University of Illinois at Urbana-Champaign

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs. ...

Preguntas Frecuentes

  • Una vez que te inscribes para obtener un Certificado, tendrás acceso a todos los videos, cuestionarios y tareas de programación (si corresponde). Las tareas calificadas por compañeros solo pueden enviarse y revisarse una vez que haya comenzado tu sesión. Si eliges explorar el curso sin comprarlo, es posible que no puedas acceder a determinadas tareas.

  • Cuando compras un Certificado, obtienes acceso a todos los materiales del curso, incluidas las tareas calificadas. Una vez que completes el curso, se añadirá tu Certificado electrónico a la página Logros. Desde allí, puedes imprimir tu Certificado o añadirlo a tu perfil de LinkedIn. Si solo quieres leer y visualizar el contenido del curso, puedes participar del curso como oyente sin costo.

¿Tienes más preguntas? Visita el Centro de Ayuda al Alumno.