Okay, so that was the signals, and well, I will not spend a lot of time for JTAG, you might know that anyways. So each core that you have has this kind of TAP controller, especially the older ones. And inside such a TAP controller there is the state machine. So, you can really see and when you hear the keyword, or the expression daisy chain, then you know, okay, that is a serial connection. And that comes in with TDI and goes out with TDO. So the bits come here inside and then it's a TMS. The mode selection we'll say, if it goes into the data register path or in the instruction register path. And when you take a look, all that looks like the real communication on drains like all looks like this. So TMS decides which way it goes. Usually I think we can see that here, the 0 means you staying this way. So if it is a loop, you stay this way. If it is straight forward, or branching, then 0 means you go straight forward. And so that's TMS. And so TMS is deciding how it continues, and TDI brings the data bits. TDO is the result, and then TDO here at the end will have a value. And with such info, we see if it works correctly, if there is an acknowledge also. And on the bit level it looks like this, and that is a real example from a customer. Well, we have many customers who are creating chips. They are developing them, designing them, and then something happens like here TDO, [SOUND] one line. Same here, the blue line TDO, it says even it's tri-stated high impotence or high resistance and it keeps one line. So that JTAG interface is simply not working. So that is such a TDI TDO chain and we will later see core side. Core side is a newer technology because if such a device here, a TAP or this one here, if that is powered down, then the whole train is broke, no communication anymore. But when we want to communicate and it's done by serial bit shifting. Then we need to know how long do we need to shift and on which position needs to be the data, the load data? So we need to know the chip, how it is constructed, or especially with the modern chips, you say simply let's say cortex A53 or so, and snapdragon whatever it is, for example. That is like a generic core. It doesnt really tell if there is something around on SRC so there could be something around. And so we usually, the call side system has depth controllers, debug access port, so we need to know where the DAP is. So in this change the DAP would be here at the end. Well, at the end is what you first think but it's at, according to the JTAG definition, EDO is where the information comes from. So TDO is where you start looking and so this is the first device and everything else here is post, yeah? Or another way, the DAP TAP is pre to this on interest. [LAUGH] Okay, so here this is our DAP. A post 16, 16 that is 9 plus 7 is 16. And DAP, debug post. That means the bypass. So the bypass bits is counting the devices, and it's a 3, 1, 2, 3 posts on the left side. So that's how it works. And we need to know that. So we have the values here. 16 and 3. And for the ETB, which is here, we have different values. There we have post and pre. Okay, that is the way how we control by a JTAG. And that's also necessary for setting up the trace that it works correctly. We heard that the trace are since signals are only available by GPIOs which are multiplex. So you need to have an influence on the target, how it should work. Okay, so we have here the overview for cross-site system. Now, our JTAG developer comes from this side here, from this line. And there is having access to the DAP, debug access port. And inside the DAP, there are memory access ports, mem AP, and there are several of them. Let's say three of them is the typical thing that you see every day and so it is also really separated. There might be one which goes to the AHP bus. Advanced high speed or high performance bus, and the other one is the advanced peripheral bus, APB. Now, the general way how it is handled is usually that the debug instructions that the debug sensed go via the APB. There's one typical case where it's never this way, that's Cortex-M. Cortex-M does it a different way, Cortex-M does also the debug excess where the AHB. Okay, besides this exception It looks usually like this and if you have legacy devices like ARM 9 and DSP and something like this which really need the JTAG access, then you can do it for as a JTAG access port. And so also here we need some information, so memory access port. You work access port and you see memory access port 0 AHP. So memory accesses will be done by AHP. While the debug access port, will be done here same address via the APB. And you'll see, there's not really, according to the board or the half, we have two entries here. We call them base address, so that's DAP:0X and then something 80 million, blah-blah. So that is for, really, debug access and then we have BMC, benchmark counter and something more. And here, already the trace part starts, and there's much more. So where do we get this information from? There are two typically ways how I get the information. All right, here is a spot. One is that we know it already, this chip, totally from the manufacturer. And so we have the information and we enter it into our software. And as soon as you select the tip, the core, then we put the values already there. That's easy, but we need to know it. Also we support many customers who are developing the tips or have the tips before we could implement them on a software. Many of our customers nowadays start with generic part like Cortex A9, or Cortex A53, and so we do not know specifically which addresses are valid. And then, we have the possibility with our debugger to access here wire the APB, the ROM table. Inside the ROM table we find the addresses. We find the AP numbers first, and then we access them and we find the ROM table. And sometimes they have sub-ROM tables also. And when we have these values, we can try to make it like automatically or we display it for the user, or I can enter some diag commands and I see it, diagnosis commands. And then I enter it. And we have some support so we can quickly create script files. So you run the script files and the values are set. That's the preparation part that's necessary for tracing, just checking if there is something else. Well, just the names, so you heard them, and later, you see them, yeah? So evac base register we have here. We have the ETM and trace micro cell. We have a different trace that's a hypertrace macrocell. We have instrumentation ITM. We have the funnel. You would see that. We have TPLU. This is really the hardware interface to the outside where we take the trace signals. And we have ETB, embedded trace buffer. So that is really on target side a little RAM where trace data can be stored. Cross trigger interface for your information. ARMv7 Is optional to use the cost trigger interface for debugging here. You can use it if you want to trigger something between devices. Then you need to set it up. But for debugging, you don't need it. If you go to v8, then you need, its mandatory to set up the cross trigger interface because with ARMv8 it's started. That debugging, single stepping, go, break, everything is controlled by this cross trigger interface. Okay, the ROM table we had already, so that is the part that I wanted to tell you. It is basic, but it's important. Who saw something like this before? You didn't see the closeup. Okay, it's really important, so take this document, and when you forget it, read it the second time and so on. Because that is the technology nowadays. Okay, so it's mandatory. Also, sometimes if you want to debug and just reading some memory, because then, as it comes into play with APB or AHB, you can go different ways. And these names are vertically related to bus masters. So they might have a different address mapping. So only covering a certain address range or so, and it might be different. So you will see that we have this in as a memory class APV and AHP in it's own exide.
