Okay. That is what I said. He was later see more of these devices that we saw in the CoreSight diagram. So, you have cores, let's say it's a duracore and each one of them has Embedded Trace Macrocell. Beside this, there might be a System Trace Macrocell also. So, these trace sources, we call them, they are merged together. So here funnels and they can be cascaded and finally you have a Trace Port Interface Unit. This is a little bit simple way to show it but it shows you how the trace data is flowing and funnelled and that the funnels have zero and one and zero and seven as the ports. To know which way we need to go inside the CoreSight system to fetch data and to retrieve it, we need to know the setup. Once again, if we select the CPU like here on map 4430, then we do this automatically, you don't need to do that and we do it with our software. But internally, it looks like this, we set up here the base address for debugging for two cores here, one, two. Typically, it's always like there are 1,000 or 10,000 difference or something, so it's quite easy to handle. And benchmark counter, Embedded Trace Macrocell system, trace macrocell one and is defining the type of it also. Then, the funnels, so we have funded one and funnel two. We have funnel one, funnel two and they have control addresses and then the funny game starts. So we have ETMs, two of them and the ETMs go here. That are the ETMs, zero goes to port zero and one goes to port one of the funnel. So here, this describes funnel one. The next funnel is two and it takes the STM on port seven and the funnel one is connected to funnel two by port zero here again. Funnel two is finally the one, is the ATB source, the advanced trace pass source for the TPIU. So it describes the full system and this way we know how to access this the right way and we pick always the right data. This nice overview you see also here is the abbreviations once more and it explains that we have here a multi-core system of Cortex-A9. That is really on map 4430 I think. I think it is online. You see already here that we have different trace sources. So not only like ETM, STM what we saw, we have also here a specific DSP, ETM from the TIA, DSP and we have PTM. Anybody an idea what PTM means? That's a Program Trace Macrocell and it's the specific first world program. Program means it excludes data. So Cortex-A9 does not have data. So when you are tracing, you have only program execution. Now, that's a little bit early to talk about but if you are tracing on a real-time operation system on your target, then it's switching and there are different task IDs or threats and so on. So, how do you separate it if there's no data coming? It's just always only addresses that you can recalculate by program execution. Well, the newer chips or the CoreSight chips, they have what's called a Context ID. So the Context ID is something specific and it's broadcasting the necessary information about when there was a task switch. So PGM is in a certain way good enough and that all this trace sources, they go into the funnel, to the advanced trace bus. For sure, if you mix them they are like interlaced then, you need to separate them somehow again to have the right data for a certain core which means they need to have Trace IDs. Usually, they are just incremented indexes in a system. So- [inaudible] Yes, the trace logic. So the PTM and the ETM and all of them, they are sent- yeah, was to funnel. I am not so sure if it is here already or there. So at least here before they are merged together, its needs to be the index that's enables us to separate them again. This one is not separating by sources, here are the sources, the red ones, this is separating now by destinations. So, it's called replicator and it separates the trace stream to go to the external trace interface, Trace Port Interface Unity TPIU, trace port or it goes to any kind of internal trace. If it is the ETB, then this is small buffer on chip. If you would have instead of ETB, SRAM, regular SRAM, on your target where you want to put the trace as a sink, then you would need one more device in between that would be the ETR, an ETR would connect to the AXI. So this here not necessary and not available with this device. So, its not shown but same like you have here, lets say the replicator, there would be one more device ETR and it would go to the AXI bus. Yeah. I have many diagrams but they are not so nice to show. They are from engineering, from the chip manufacturers and they are very confusing with upscale or downscale 32-bit to 64-bit and so on. So this one is better for presentation. Okay. Well, ETM is the development, let's say, or was invented, defined to have execution information. Let's say 20-30 years ago, you had processors and they had external memory and external devices and so if you had- it's really a processor, the CPU only, no system on-chip, just the CPU then the CPU had for sure all the address lines and data lines outside. So, that was what we called a Bus Trace and you just needed to steal the info and it was good. But now with the ETM, that is a protocol, that is the interface. There is no bus system anymore in this normal way, it's a protocol. So, how to define this protocol and here we see ETM version one had Trace Synchronization, pipe state and so on and then the data and you needed to really to read the data even backwards and then you could recalculate the address that was sent. So, it was terrible and you see with each line here has like two bytes, that is almost like a Bus Trace, so it takes a lot of space and it's not fast. That is comparatively only little data. So, that is now ETM version three and here you have in each line only one byte and mostly here in France even zeros and so. So that is more compact and currently it's ETM version four even. I gave a document. So, there is a document which is also nice to see. It's a slideshow that a colleague created. It's only regarding ETM version four and shows the differences. So the PTM that we saw, just for example, not tell anymore about indirect instructions, indirect execution. So the PTM is rather restricted and the ETM version four was intended just to be better and faster. End of this. But ETM four still with all the cores that you have, Cortex-A9, Cortex-A53, they have the same type of trace interface so they still don't deliver data information. They say these cores are so fast in execution so it would be really a bottleneck to trace something that is broadcasting data information and so they simply said no data, just instructions. So that is really the basic information now and we continue with the tracing information.
