So far we have concentrated on the intrinsic part of a transistor between source and drain. We will now consider the rest of the device, the extrinsic part, and briefly talk about the elements that need to be used in order to model that part. Once we include the part of the device outside the main channel region, we see A large number of elements that have not been included so far. I will show you the picture, and I want to warn you it is a little scary, but this is what things look like. We have modeled the part between source and drain which is shown here. Now we will take a very brief tour of what is outside. This is the main source. It has some resistance. Then there is a source extension. These extensions are used to avoid having this bulky region very close to the channel in which case you would have strong uh,[INAUDIBLE] effects. This extension also has some resistance. You can think of this plus this as one source. Similarly, this is the main drain region, with some resistance. And the drain extension with more resistance. The gate, it although on top of it has[UNKNOWN] for low resistance but also has some resistance, and then when you go down through the polysilicon. To the interface with the oxide. There is some resistance associated with that region too. In the body, the body is a semiconducting region. And it has some resistance that is totally distributed. So what is done is you look at it as a long approximation to a distributed situation. So you would model it using. A resistance from the body of the device to some point in the middle of the substrate here. Some other resistance that takes you close to the drain, resistance takes you close to the source, and some resistance that takes you to the body terminal. And[COUGH] between the gate and the body there is some capacitance. Shown here. Now, let's look at this element between the n source and the p body, there is a pn junction. And the same is true between for the part between the n drain and the p body over here. Now, contacts are made to the source and drain regions using metal. These are two contacts on the, eh, on the source, and two on the drain. These contacts have some resistance associated with them, shown here, here, and here. And between them, they also have some capacitance. And also there is some capacitance between each contact and gate shown here and there. As you can see this is a large number of parasitic elements all of which can affect the behavior of the device. these are modeled by semi empirical results. People start from analytical results and then modify them in order to get. Reasonable expressions. And this has to be done in an efficient way in order to follow the rapidly evolving technology. Examples of formulas used for these elements are shown in the book. I will not show them here. I will instead discuss a couple of effects that one needs to be aware of. One is the inter, the inner fringing capacitance. When a channel has been formed, then there is capacitance between the gate and the channel, shown here. This is part of the intrinsic device, so to speak. However, when the channel is off, then the gate sees the side wall of the source directly. Okay? So this capacitance changes to this capacitance. So this is one rather subtle effect of the inner fringing capacitance. Gate resistance, when you have a device like this with a wide channel and a short channel, so W's large. L is short. And let's say you contact the gate, as you look at it from above, from only one side, like this. If you now look at the device vertically, which is the way we usually see, look at the device, we have an oxide region here. This is the channel. This is the polysilicon gate, and on top of it, you have this underside, to make sure that. The, you have a low resistance contact to the entire gate. Now when the voltages are varying the gate charge is varying and you have gate current, dq G dt, which we have already discussed. so this is a capacity type of current. This current enters here, and because there is some local capacitance between the gate and the channel, some capacity of current flows in this direction. So this minus that is left to continue flowing further to the right. Then there is another capacity of current, so even less current is left to follow the flow to the right, and so on. So although I described this as if it were a lamp situation, actually what I, the mechanisms I describe are of course totally distributed, but the net result is that the current in the horizontal dimension becomes less and less. So this is rather complicated to model. It means that, because there is not much current here, there is no not much voltage drop either. So, it is mostly the parts of the gate near the contact that matter. These ones matter less. And because of that we have to modify the resistance of the gate. You will find the formulas in the book for that. Then you have a device that is contacted not one one side but rather on two sides. That can significantly decrease the total gate resistance which is important to do at high frequencies because now you only have half of the device associated with one contact and half of the device associated with the other. So each of them, if, if the, if. Resistance here where of a certain magnitude, here you would have, let's say, rough roughly half of the resistance associated with each device. If the two resistances are effectively in parallel, so you would expect the total resistance to be one fourth of the what you had over here. This is not exactly true because of the distributive effect I described but again, I will only refer you to the book for more results. So, this is the situation we're describing. It is a messy situation full of semi-empirical results. I will not have time to discuss them here. I will just say that if we have this situation and we try to let's say, analyze a circuit by hand, it's totally hopeless. So we have to go from this to something much simpler, and what we do is this. We take the intrinsic part of the device, which we have modeled in great detail. We lump all of the gate resistance into a single gate resistance. All of the source resistance into a single one here, single drain resistance, a single body resistance, and then we allow for capacitances between any two parts of the structure. So for example, and I should have mentioned it before. Between the gate and the source, there is a capacitance, cts. Between the gate and the drain, there is a capacitance also. And this is because the gate overlaps the source and drain regions. So, these are the overlap capacitances. We lump them all in one capacitance between gate and source, and e stands for extrinsic. Another capacitance takes care of the gate to drain extrinsic capacitance. Then we have a junction capacitance between body and source, Cbse, a junction capacitance between body and drain, Cbde, a single body resistance here, some capacitance between source and drain. And if this device is residing inside the well, we have some junction capacitance between the well and the substrate, which is shown here by Cbb prime. So at least this model is simple enough for people to derive some approximate results. And even that model is rather complicated. So, in particular situations, you may want to even simplify this further. When we discuss small signal effects, we will show particular cases of this and how it can be simplified. So in this very brief video, I introduce you to the messy situation of extrinsic[UNKNOWN] . Which of course we do not have a time to cover in detail, I refer you to the book for more details. At this point we have finished with our large signal dynamic operation and in the next series of lectures we will be talking about small signal modeling.